View CY7C1512-20ZI_839817.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1CY 7C15 12
PRELIMINARY
CY7C1512
64K x 8 Static RAM
Features
* High speed -- tAA = 15 ns * CMOS for optimum speed/power * Low active power -- 770 mW * Low standby power -- 28 mW * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1512 is available in standard TSOP type I and 450-mil-wide plastic SOIC packages.
Functional Description
The CY7C1512 is a high-performance CMOS static RAM organized as 65,536 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active LOW output enable (OE),
Logic Block Diagram
Pin Configurations
SOIC Top View
NC NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A11 A9 A8 A13 WE CE2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7
I/O1 I/O2
64K x 8 ARRAY
1512-2 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
I/O3 I/O4 I/O5
POWER DOWN
CE 1 CE2 WE
COLUMN DECODER
I/O6 I/O7
1512-1
TSOP I Top View (not to scale)
OE
Selection Guide
Maximum Access Time (ns) Maximum Operating Commercial Current (mA) Maximum CMOS Commercial Standby Current (mA) 7C1512-15 15 140 5 7C1512-20 20 130 5 7C1512-25 25 120 5 7C1512-35 35 110 5 7C1512-70 70 110 5
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 June 1996 - Revised October 1996
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage[1]..................................-0.5V to VCC +0.5V Electrical Characteristics Over the Operating Range[3] 7C1512-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit VCC Operating Supply Current Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs Current[4] GND < VI < VCC GND < VI < VCC,Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC - 0.3V, or CE2 < 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC - 0.3V, or CE2 < 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 -1 -5 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 -300 110 25 2.2 -0.3 -1 -5 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 0.4 2.2 -0.3 -1 -5 VCC + 0.3 0.8 +1 +5 -300 140 40 2.2 -0.3 -1 -5 Max. 7C1512-20 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 130 30 Max.
CY7C1512
Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
7C1512-25 Min. 2.4 0.4 2.2 -0.3 -1 -5 VCC + 0.3 0.8 +1 +5 -300 120 30 Max. Unit V V V V A A mA mA mA
ISB2
5
5
5
mA
7C1512-35 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs Max.
7C1512-70 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 -300 110 25 Max. Unit V V V V A A mA mA mA
ISB2
5
5
mA
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
PRELIMINARY
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 9
CY7C1512
Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT R2 255 R1 480 R1 480 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND <3ns 3.0V 90% 10% 90% 10% < 3 ns ALL INPUT PULSES
1512-3 1512-4
THVENIN EQUIVALENT 167 1.73V
Switching Characteristics [3, 6] Over the Operating Range
7C1512-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
5. 6. 7. 8. 9.
7C1512-20 Min. 20 Max.
7C1512-25 Min. 25 Max. Unit ns 25 5 25 10 0 10 5 10 0 25 25 20 20 0 0 20 15 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7, 8] CE1 LOW to Low Z, CE2 HIGH to Low Z[8] CE1 HIGH to High Z, CE2 LOW to High Z[7, 8] CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[7, 8]
Min. 15
Max.
15 3 15 7 0 7 3 7 0 15 15 12 12 0 0 12 8 0 3 7 20 15 15 0 0 15 10 0 3 0 3 0 3
20 20 8 8 8 20
WRITE CYCLE[9]
8
Tested initially and after any design or process changes that may affect these parameters. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
PRELIMINARY
Switching Characteristics[3, 6] Over the Operating Range (continued)
7C1512-35 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7, 8] 5 15 0 35 35 25 25 0 0 25 20 0 5 15 70 60 60 0 0 60 55 0 5 0 Z[7, 8] CE1 LOW to Low Z, CE2 HIGH to Low Z[8] CE1 HIGH to High Z, CE2 LOW to High CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down CYCLE[9] Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[7, 8] 0 15 5 5 35 15 0 35 35 5 70 Description Min. Min.
CY7C1512
7C1512-70 Min. Min. Unit ns 70 70 15 15 15 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1512-5
Notes: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle.
4
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD
CY7C1512
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
1512-6
Write Cycle No. 1 (CE1 or CE2 Controlled) [13, 14]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA
WE tSD DATA I/O DATA VALID
1512-7
tHD
Notes: 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
5
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
CY7C1512
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE t HA
OE tSD DATA I/O NOTE 15 tHZOE DATA INVALID
1512-8
t HD
Write Cycle No. 3 (WE Controlled, OE LOW)
[14]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tLZWE
1512-9
tHA tPWE
tHD
Note: 15. During this period the I/Os are in the output state and input signals should not be applied.
6
PRELIMINARY
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z Mode Power-Down Power-Down Read Write Selected, Outputs Disabled Power Standby (I SB) Standby (I SB) Active (ICC) Active (ICC) Active (ICC)
CY7C1512
Ordering Information
Speed (ns) 15 Ordering Code CY7C1512-15SC CY7C1512-15ZC CY7C1512-20ZI 20 CY7C1512-20SC CY7C1512-20ZC CY7C1512-20ZI 25 CY7C1512-25SC CY7C1512-25ZC CY7C1512-25ZI 35 70 CY7C1512-35SC CY7C1512-70SC CY7C1512-70ZC CY7C1512-70ZI
Shaded areas contain advanced information.
Package Name S34 Z32 Z32 S34 Z32 Z32 S34 Z32 Z32 S34 S34 Z32 Z32
Package Type 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I 32-Lead TSOP Type I 32-Lead (450-Mil) Molded SOIC 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I 32-Lead TSOP Type I
Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Commercial Industrial
Document #: 38-00522-A
7
PRELIMINARY
Package Diagrams
32-Lead (450 -Mil) Molded SOIC S34
CY7C1512
32-Lead Thin Small Outline Package Z32
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY7C1512-20ZI

	To Download CY7C1512-20ZI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .